1. Field of the Invention
The present invention relates to a semiconductor device and particularly relates to a semiconductor device with a multiple power sources, which is operated with a plurality of power sources. More specifically, the present invention relates to an embedded memory integrated on a common semiconductor chip with a logic circuit. More particularly, the present invention relates to the construction of internal voltage generation circuitry of an embedded memory.
2. Description of the Background Art
Recently, system LSI's (large scale integrated circuits) each having a logic circuit and a large storage capacity DRAM (dynamic random access memory) integrated on the same semiconductor substrate are widely used.
FIG. 36 is a schematic diagram showing a construction of a power source of a conventional system LSI. In FIG. 36, the system LSI includes a logic LG such as a processor and a DRAM macro DM serving as a main memory for logic LG.
DRAM macro DM includes a memory cell array MA having memory cells arranged in a matrix of rows and columns, a sense amplifier SA sensing, amplifying and latching the data of memory cells connected to a selected row in memory array MA, a row decoder RD selecting an addressed row in memory cell array MA, a control circuit CTL controlling the internal operation of DRAM macro DM, and an internal voltage generation circuit IVGA receiving an external power supply voltage VDDH and generating internal voltages VDDS, VPP and VBB.
Internal voltage VDDS is used as the operating power supply voltage of sense amplifier SA. Sense amplifier power supply voltage (or array power supply voltage) VDDS determines the H voltage level of data stored in a memory cell in memory cell array MA.
Internal voltage VPP is transmitted to a word line arranged corresponding to the selected row in memory cell array MA through row decoder RD. The voltage (boosted voltage) VPP is generated by boosting external power supply voltage VDDH through, for example, a charge pumping operation.
Internal voltage VBB is a negative voltage and applied, as a bias voltage, to the substrate region of memory cell array MA. Substrate bias voltage VBB allows the threshold voltage of each memory cell transistor formed in memory cell array to be stabilized and the junction capacitance of the memory transistor to be reduced.
An external power supply voltage VDDL is applied to logic LG and control circuit CTL. Since MOS transistors (insulated gate type field effect transistors) used in logic LG and control circuit CTL in DRAM macro DM are normally operated at high speed, the absolute values of the threshold voltages of the MOS transistors are set smaller than the absolute values of the threshold values of MOS transistors used in the memory cell array MA of DRAM macro DM. For a MOS transistor used in logic LG, in particular, a MOS transistor (low Vth transistor) having a small absolute value of the threshold voltage is employed in view of high speed operability and low power consumption. Therefore, the MOS transistor in logic LG causes a large leak current (large off-leak current) when being turned off.
Meanwhile, the MOS transistor used in control circuit CT in DRAM macro DM is not required to be operated at high speed, compared with the MOS transistor of logic LG. Thus, the MOS transistor included in control circuit CTL at periphery of the memory cell array may be greater in absolute value of the threshold voltage than the MOS transistor in logic LG (referred to as “logic transistor” hereinafter). However, if the MOS transistor having the absolute value of the threshold voltage different from that of the logic transistor is used in control circuit CTL, it is necessary to manufacture the logic transistor of logic LG and the MOS transistor of control circuit CTL in individual different manufacturing steps, which disadvantageously increases manufacturing cost.
For that reason, the logic transistor is also used for control circuit CTL. That is, a MOS transistor equal in size (equal in gate insulating film thickness) to the MOS transistor used for logic LG is used as the MOS transistor for control circuit CTL. Thus, the logic transistor is used as the MOS transistor for control circuit CTL, and therefore, the standby current in control circuit CTL in DRAM macro DM disadvantageously increases and low current consumption cannot be achieved.
The gate insulating film thickness of the logic transistor is made small for the purpose of reducing the threshold voltage, and the gate insulating film thickness of the MOS transistor is generally determined according to an applied power supply voltage. Therefore, power supply voltage VDDL applied to logic LG and control circuit CTL (referred to as “logic power supply voltage” hereinafter) is made lower than power supply voltage VDDH applied to DRAM macro DM (referred to as “memory power supply voltage” hereinafter).
FIG. 37A shows an example of the construction of a logic element included in logic LG. FIG. 37A representatively shows a CMOS (complementary MOS) inverter as a typical component of the logic. In FIG. 37A, the CMOS inverter of logic LG includes a P channel MOS transistor PQ1 connected between a logic power source node and an output node, having a gate receiving an input signal IN and having a back gate (substrate region) connected to the logic power source node, and an N channel MOS transistor NQ1 connected between the output node and a ground node, having a gate receiving the input signal IN and having a back gate (substrate region) connected to the ground node. Logic power supply voltage VDDL is supplied to the logic source node and a ground voltage GND is supplied to the ground node.
Each of logic transistors PQ1 and NQ1 shown in FIG. 37A has a small absolute value of the threshold voltage and also has a gate insulating film made thin in accordance with, for example, a predetermined scaling rule, for shrinking of the transistor size.
FIG. 37B is a schematic diagram showing the cross sectional structure of the CMOS inverter shown in FIG. 37A. In FIG. 37B, P channel MOS transistor PQ1 is formed at the surface of an N well 1000 biased to a logic power supply voltage VDDL level through an N type impurity region 1001. P channel MOS transistor PQ1 includes P type impurity regions 1002 and 1003 formed spaced from each other on the surface of N well 1000, and a gate electrode 1004 formed on the well region between impurity regions 1002 and 1003 with a not shown gate insulating film interposed below.
Impurity region 1002 is supplied with logic power supply voltage VDDL, and impurity region 1003 is coupled to the output node for generating an output signal OUT. Gate electrode 1004 is supplied with input signal IN. Impurity region 1002 serves as a source region.
N channel MOS transistor NQ1 is formed on the surface of a P well 1010 biased to a ground voltage GND level through a P type impurity region 1001. N channel MOS transistor NQ1 includes N type impurity regions 1012 and 1013 formed to be away from each other on the surface of P well 1010, and a gate electrode 1014 formed on the well region between impurity regions 1012 and 1013 with a not shown gate insulating film interposed in between.
Impurity region 1012 is connected to the ground node, and serves as a source. Impurity region 1013 is connected to the output node. Gate electrode 1014 receives input signal IN.
As shown in FIGS. 37A and 37B, the high speed operation of each of MOS transistors PQ1 and NQ1 can be achieved by connecting the source to each respective back gate and suppressing a substrate bias effect.
FIG. 38A is a circuit diagram showing the electrically equivalent circuit of the P channel MOS transistor employed in memory cell array MA and sense amplifier SA in DRAM macro DM. In FIG. 38A, a P channel MOS transistor PQ2 has a source receiving array power supply voltage VDDS and a back gate receiving boosted voltage VPP. The gate of MOS transistor PQ2 is supplied with a voltage having an amplitude determined according to application. For example, if P channel MOS transistor PQ2 is an MOS transistor included in sense amplifier SA shown in FIG. 36, the gate thereof is connected to a bit line of memory cell array MA and the voltage level of the bit line is driven to the ground voltage level, precharge voltage level or array power supply voltage level. When MOS transistor PQ2 is rendered conductive, array source voltage VDDS is transmitted to the drain thereof. By applying boosted voltage VPP to the substrate region, the absolute value of the threshold voltage of the transistor PQ2 is made great, the influence of the noise of array source voltage VDDS is reduced to prevent a P channel MOS transistor, which should be kept off, from being turned on.
If P channel MOS transistor PQ2 is included in a word driver transmitting boosting voltage VPP to a selected word line, the source of the transistor PQ2 is supplied with boosted voltage VPP or receives a signal having an amplitude of VPP in place of array power supply voltage VDDS. Even if the P channel MOS transistor is used in such a word driver, the source attains a boosted voltage level at maximum, so that boosted voltage VPP is applied to the substrate region (back gate) thereof.
FIG. 38B is a circuit diagram showing the electrically equivalent circuit of N channel MOS transistor NQ2 employed in memory cell array MA and sense amplifier SA. In FIG. 38B, the source of N channel MOS transistor NQ2 is connected to the ground node and the back gate thereof receives a substrate bias voltage VBB. The gate of the transistor NQ2 is supplied with a signal of an amplitude determined according to application. MOS transistor NQ2 supplies ground voltage GND to the drain when being conductive.
Substrate bias voltage VBB is applied to the back gate of an access transistor of a memory cell included in memory cell array MA. If N channel MOS transistor NQ2 is used as the access transistor of the memory cell, the drain/source thereof is connected to a storage node storing information and source/drain is connected to a bit line. Here, the source and drain of the MOS transistor are exchanged in position according to their respective voltage levels.
If N channel MOS transistor NQ2 is used in the word driver, the back gate thereof receives a negative voltage to set the threshold voltage high, whereby N channel MOS transistor NQ2 is reliably set in an off state without an influence of ground node noise.
Normally, boosted voltage VPP is at the voltage level of a voltage transmitted onto word lines WL's arranged corresponding to the rows of the memory cells in memory cell array MA. N channel MOS transistor shown in FIG. 38B is used in, for example, a word driver for driving a word line into a select state.
As shown in FIGS. 38A and 38B, it is intended, by deepening the back gate bias of the MOS transistor, to stabilize the threshold voltage and to enhance power source noise immunity.
A logic element having the same construction as that shown in FIG. 37A is used in control circuit CTL. In this case, the off-leak current of the MOS transistor increases. Therefore, a countermeasure for increasing the absolute value of the threshold voltage of the MOS transistor by deepening the well bias so as to reduce the off-leak current, is normally used.
FIG. 39 shows an example of the construction of a logic element included in control circuit CTL shown in FIG. 36. In FIG. 39, the logic element of control circuit CTL has the construction of a CMOS inverter formed of a P channel MOS transistor PQ3 and an N channel MOS transistor NQ3. Boosted voltage VPP is applied to the back gate of P channel MOS transistor PQ3 from a VPP generation circuit 1020 and negative voltage VBB is applied to the back gate of N channel MOS transistor NQ3 from a VBB generation circuit 1030. Negative voltage VBB may be the same as or different from substrate bias voltage VBB applied to the substrate region of memory cell array MA. In the following description, therefore, internal voltage VBB will be simply referred to as “negative voltage”.
The source of P channel MOS transistor PQ3 is connected to the logic power source node and the source of N channel MOS transistor NQ3 is connected to the ground node. VPP generation circuit 1020 and VBB generation circuit 1030 are included in internal voltage generation circuit INVG shown in FIG. 36. VPP generation circuit 1020 and VBB generation circuit 1030 receive memory power supply voltage VDDH as an operating power supply voltage and generate boosted voltage VPP and negative voltage VBB through, for example, a charge pumping operation, respectively.
Boosted voltage VPP is higher in level than logic power supply voltage VDDL and negative voltage VBB is lower in level than ground voltage GND. Accordingly, the back gate biases of MOS transistors PQ3 and NQ3 are deeper than that of a transistor having a back gate and a source connected together. As a result, the absolute values of the threshold voltages of MOS transistors PQ3 and NQ3 becomes greater, thereby making it possible to reduce off-leak current. Therefore, by using a logic transistor having the same structure (same in gate insulating film thickness and material) as that of the transistor included in logic LG, in DRAM macro DM and deepening the bias of the back gate of the transistor, it is possible to reduce off-leak current and to achieve low standby current accordingly. Also, the transistor of control circuit CTL and the transistor of logic LG can be manufactured in the same manufacturing steps to reduce manufacturing cost.
FIG. 40 is a schematic diagram showing the cross sectional structure of the CMOS transistor included in control circuit CTL of the DRAM macro shown in FIG. 39. In FIG. 40, MOS transistor PQ3 is formed in an N well 1040 and N channel MOS transistor NQ3 is formed in a P well 1050. N well 1040 is supplied with boosted voltage VPP from VPP generation circuit 1020 through an N type impurity region 1041. P well 1050 is supplied with negative voltage VBB from VBB generation circuit 1030 through a P type impurity region 1051.
P channel MOS transistor 1040 includes P type impurity regions 1042 and 1043 formed, spaced from each other, on the surface of N well 1040 and a gate electrode 1044 formed with a not shown gate insulating film interposed in between on the surface of the N well region between impurity regions 1042 and 1043.
N channel MOS transistor NQ3 includes N type impurity regions 1052 and 1053 formed, spaced from each other, on the surface of P well 1050 and a gate electrode 1054 formed with a not shown gate insulating film interposed in between on the surface of the P well region between impurity regions 1052 and 1053.
Impurity region 1042 receives logic power supply voltage VDDL and impurity region 1052 receives ground voltage GND. Impurity regions 1043 and 1053 are coupled to an output node and gate electrodes 1044 and 1054 receives input signal IN.
In the construction of the CMOS inverter shown in FIG. 40, a parasitic PNP bipolar transistor Q1 having an emitter formed of P type impurity region 1042, collector formed of P type impurity region 1043 and P well 1050 and a base formed of N well 1040, is formed in N well 1040. A parasitic diode D1 is formed between P type impurity region 1042 and N type impurity region 1041. A resistance R1 produced by the substrate resistance of N well 1040 exists between the base region of parasitic PNP bipolar transistor Q1 and the cathode (node n1) of parasitic diode D1.
On the other hand, a parasitic NPN bipolar transistor Q2 having N type impurity region 1052 serving as an emitter, P well 1050 serving as a base region and N well 1040 serving as a collector, is formed in P well 1050. Negative voltage VBB is applied to the base of parasitic NPN bipolar transistor Q2 from impurity region 1051 through a resistance R2.
If the parasitic bipolar transistors stated above exist and logic power supply voltage VDDL is applied before application of memory power supply voltage VDDH, VPP generation circuit 1020 and VBB generation circuit 1030 are not operated and therefore, boosted voltage VPP and negative voltage VBB are not generated. Under such condition, each of VPP generation circuit 1020 and VBB generation circuit 1030 is in an output high impedance state (i.e., the charge transferring MOS transistor at the output stage of each circuit is kept off). Thus, although boosted voltage VPP is not generated, the level of the well potential fixing node n1 (impurity region 1041) of P type MOS transistor PQ3 becomes a potential level of a voltage (VDDL-φb) because of the presence of parasitic diode D1. Here, φb denotes the diffusion potential of parasitic diode D1.
The potential of N well potential fixing node n1 is applied through parasitic resistance R1 to a node n2. A voltage drop substantially equal to the forward voltage drop between the base and emitter of parasitic bipolar transistor Q1 is caused due to parasitic diode D1. Further, a voltage drop occurs through parasitic resistance R1. Thus, the emitter to base region of parasitic bipolar transistor Q1 is forwardly biased and a current Ic1 flows between the emitter and the collector of parasitic bipolar transistor Q1.
Collector current Ic1 of parasitic bipolar transistor Q1 causes base electrode node n3 of parasitic NPN bipolar transistor Q2 to have a positive potential level higher than the ground voltage level. If base electrode node n3 has a positive potential, then the base to emitter region of parasitic bipolar transistor Q2 is forwardly biased, parasitic bipolar transistor Q2 becomes conductive and a collector current Ic2 flows between the collector and the emitter of parasitic bipolar transistor Q2. Parasitic bipolar transistor Q2 receives collector current Ic1 supplied from parasitic bipolar transistor Q1 as a base current. Collector current Ic2 which is ‘hfe’ times the collector current Ic1, flows through parasitic bipolar transistor Q2 from the logic source node through impurity region 1042, well potential fixing node n1 and internal node n2, and collector current Ic2 further flows to the ground node through impurity region 1052.
Accordingly, if a thyristor formed of parasitic bipolar transistors Q1 and Q2 is turned on, a large current flows into impurity region 1052 coupled to the ground node from impurity region 1042 coupled to the logic source node. If parasitic bipolar transistors Q1 and Q2 perform a thyristor operation, i.e., a so-called “latch-up phenomenon” occurs, the thyristor operation cannot be stopped thereafter even by applying memory power supply voltage VDDH and generating boosted voltage VPP and negative voltage VBB. If this “latch-up phenomenon” occurs, a large current flows due to the thyristor operation of these parasitic bipolar transistors, and the MOS transistors may be destructed or a signal interconnection line may be cut off due to generated heat. If such a latch-up phenomenon occurs, it is only possible to stop the thyristor operation by shutting off the supply of the power supply voltage. However, it is impossible to instantly identify externally whether or not the latch-up phenomenon occurs internally.
For the system LSI as stated above, if a plurality of power sources are employed and the DRAM core is driven with the plural power supply voltages, a power application sequence is not predetermined in the specification. In practical use, the order of applying memory power supply voltage VDDH and logic power supply voltage VDL is variously set, and therefore, there is a possibility of the occurrence of the latch-up phenomenon as described above. Therefore, a construction in which the peripheral circuit of the DRAM macro is formed of the logic transistors having the back gate bias thereof adjusted to increase the absolute value of the threshold voltage cannot be employed. As a result, the logic transistor cannot be used for the control circuit at the peripheral circuit of the DRAM macro and manufacturing cost cannot be reduced. Besides, if the logic transistor is used for the DRAM peripheral control circuit, a well bias cannot be adjusted and therefore, the standby current cannot be reduced.